This page lists all content on our site that has been tagged with "Electronic digital computers". You may find a variety of content here, from books, to exhibitions, to events.

Pages

Image Gallery

Smithsonian Libraries content listing by subject terms
A.C. power distribution rack. PX-1-304

A.C. power distribution rack. PX-1-304

Accumulator front panel PX-5-301 R

Accumulator front panel PX-5-301 R

Accumulator front view. PX-5-305

Accumulator front view. PX-5-305

Accumulator Interconnection Diagram. PX-5-302

Accumulator Interconnection Diagram. PX-5-302

Activation of Render Programming Circuits in Reading Detail ...

Activation of Render Programming Circuits in Reading Detail ...

Constant transmitter front panel No. 1 PX-11-302 R

Constant transmitter front panel No. 1 PX-11-302 R

Constant transmitter front panel no. 2 PX-11-303 R

Constant transmitter front panel no. 2 PX-11-303 R

Constant transmitter front panel no. 3 PX-11-304 R

Constant transmitter front panel no. 3 PX-11-304 R

Constant transmitter front view PX-11-306

Constant transmitter front view PX-11-306

Constant Transmitter Interconnection Diagram. PX-11-301

Constant Transmitter Interconnection Diagram. PX-11-301

Cycling unit front panel PX-9-303 R

Cycling unit front panel PX-9-303 R

Cycling unit front view. PX-9-304

Cycling unit front view. PX-9-304

Cycling Unit Pulses & Gates PX-9-306

Cycling Unit Pulses & Gates PX-9-306

Deleters. PX-4-109

Deleters. PX-4-109

Div. Interconnection Diagram, PX-10-303

Div. Interconnection Diagram, PX-10-303

Divider and square rooter front panel PX-10-301 R

Divider and square rooter front panel PX-10-301 R

Divider-square rooter front view PX-10-302

Divider-square rooter front view PX-10-302

Fig 8-3 (a). Set-up diagram for sequence 1 and sequence 2.1. PX-11-405 (a)

Fig 8-3 (a). Set-up diagram for sequence 1 and sequence 2.1. PX-11-405 (a)

Fig 8-3 (d) Set-up diagram for sequence 1 and sequence 2.1

Fig 8-3 (d) Set-up diagram for sequence 1 and sequence 2.1

Fig. 10-1. Use of master programmer to stimulate ...

Fig. 10-1. Use of master programmer to stimulate ...

Fig. 10-2 (a) Digit discrimination program ... PX-8-402a

Fig. 10-2 (a) Digit discrimination program ... PX-8-402a

Fig. 10-2 (b). Digit discrimination program ... Master programmer panel 2. PX-8-402 b

Fig. 10-2 (b). Digit discrimination program ... Master programmer panel 2. PX-8-402 b

Fig. 10-2 (c). Digit discrimination program to stimulate ...

Fig. 10-2 (c). Digit discrimination program to stimulate ...

Fig. 10-3. Us of a master programmer to delay a program pulse

Fig. 10-3. Us of a master programmer to delay a program pulse

Fig. 10-4. Master programmer set-up diagram conventions

Fig. 10-4. Master programmer set-up diagram conventions

Fig. 10-6. Set-up diagram - problem 1. Master programmer panel 1. PX-8-404

Fig. 10-6. Set-up diagram - problem 1. Master programmer panel 1. PX-8-404

Fig. 10-8. Master programmer links - problem 2

Fig. 10-8. Master programmer links - problem 2

Fig. 10-9 (a). Set up diagram for tests ... Master programmer panel 2

Fig. 10-9 (a). Set up diagram for tests ... Master programmer panel 2

Fig. 10-9 (b). Set-up diagram for tests ...

Fig. 10-9 (b). Set-up diagram for tests ...

Fig. 10-9 (c). Set up diagram for tests ...

Fig. 10-9 (c). Set up diagram for tests ...

Fig. 11-2. Bidirectional communication in pulse amplifier connected trays

Fig. 11-2. Bidirectional communication in pulse amplifier connected trays

Fig. 11-3. Isolation of programs through the use of a pulse amplifier

Fig. 11-3. Isolation of programs through the use of a pulse amplifier

Fig. 4-1. Set-up diagram symbols for accumulator

Fig. 4-1. Set-up diagram symbols for accumulator

Fig. 4-2. Set-up diagram for problem of generating n ...

Fig. 4-2. Set-up diagram for problem of generating n ...

Fig. 4-3. Use of dummy programs to isolate program pulses

Fig. 4-3. Use of dummy programs to isolate program pulses

Fig. 4-4. Magnitude discrimination program

Fig. 4-4. Magnitude discrimination program

Fig. 5-1. Set-up diagram conventions for high-speed multiplier

Fig. 5-1. Set-up diagram conventions for high-speed multiplier

Fig. 5-2. Master programmer lines evaluation ... PX-11-404

Fig. 5-2. Master programmer lines evaluation ... PX-11-404

Fig. 6-2 (a). Set-up diagram for computation ... Master programmer panel 1 ... PX-10 ...

Fig. 6-2 (a). Set-up diagram for computation ... Master programmer panel 1 ... PX-10 ...

Fig. 6-2 (b). Set-up diagram for computation ... PX-10-102 (b)

Fig. 6-2 (b). Set-up diagram for computation ... PX-10-102 (b)

Fig. 6-2 (c). Set-up diagram ... PX-10-402 (c)

Fig. 6-2 (c). Set-up diagram ... PX-10-402 (c)

Fig. 6-2 (d). Set-up diagram for computation ... PX-10-402 (d)

Fig. 6-2 (d). Set-up diagram for computation ... PX-10-402 (d)

Fig. 6-2 (e). Set-up diagram for computation ... PX-10-402 (e)

Fig. 6-2 (e). Set-up diagram for computation ... PX-10-402 (e)

Fig. 6-2 (f) Set-up diagram for computation ... PX-10-402 (f)

Fig. 6-2 (f) Set-up diagram for computation ... PX-10-402 (f)

Fig. 6-2 (g) Set-up diagram for computation ... PX-10-402 (g)

Fig. 6-2 (g) Set-up diagram for computation ... PX-10-402 (g)

Fig. 6-3 (b). Quadratic Lagrangian Interpolation - Set-Up Diagram ... PX-7-403 b

Fig. 6-3 (b). Quadratic Lagrangian Interpolation - Set-Up Diagram ... PX-7-403 b

Fig. 7-3 (a). Quadratic Lagrangian Interpolation - Set-up Diagram ... PX-7 ...

Fig. 7-3 (a). Quadratic Lagrangian Interpolation - Set-up Diagram ... PX-7 ...

Fig. 7-3 (c). Quadratic Lagrangian Interpolation - Set-Up Diagram ... PX-7-403 c

Fig. 7-3 (c). Quadratic Lagrangian Interpolation - Set-Up Diagram ... PX-7-403 c

Fig. 7-3 (d) Quadratic Lagrangian Interpolation - Set-up Diagram ... PX ... 403d

Fig. 7-3 (d) Quadratic Lagrangian Interpolation - Set-up Diagram ... PX ... 403d

Fig. 7-3 (e). Quadratic Interpolation ;- Set-up Diagram ... PX-7-403e

Fig. 7-3 (e). Quadratic Interpolation ;- Set-up Diagram ... PX-7-403e

Pages